Digital and analog signal conversion circuits are important circuits as it can be used in signal processing systems, image processing and communication systems. The most researchers nowadays are interested with how to reduce power dissipation, compact circuit structure, and increase the speed of conversion. This paper present two types of improved hybrid SET/MOS DAC and ADC circuits. The SET/MOS hybrid ADC and DAC circuits have the advantages of the SET circuit and the MOS circuit. The PSPICE Recursion Relation Model (RRM) with four charge states of the SET transistor was used. The improved hybrid n-bit DAC nano-circuits are simulated (for n = 4 and 8) using Orcad Capture PSPICE simulator. The performance of the SET/MOS hybrid n-bit ADC circuits were simulated (for n = 3 and 8). The results show that the proposed improved n-bit DAC and ADC nano-circuits have the advantages of high driving capability and the enhanced swing of the output signal which is better than pure SET ADC and DAC circuits. The improved n-bit DAC nano-circuits have compact circuit structure, higher integration density, high speed, high load drivability, and low-power dissipation compared with the previously reported SET/MOS hybrid DAC.
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