A fully differential CMOS sample and hold circuit (S/H) in current mode double sampling technique, gives a factor of two increase in the sampling rate while maintaining comparable power consumption and circuit complexity in comparison with the conventional S/H configuration. A precise current mirror circuit with low input impedance is adopted. A fully differential configuration for placing the switches were used to cancel the sample switches feed-through error. Also, the clock controlling the sample switches is boosted so as to make their on resistance low. The circuit is designed and simulated in 0.5 µm CMOS technology using BSIM3v3 device parameters. Simulation results shows 10-bit operation at the sampling rate of 80 sample/sec with 10mW power dissipation at 3 V supply.
El-Simary, H. (2021). A 80 MS/S CMOS Sample-and-Hold Current Mode Circuit Using Double Sampling.. MEJ- Mansoura Engineering Journal, 25(4), 42-49. doi: 10.21608/bfemu.2021.147060
MLA
Hamed El-Simary. "A 80 MS/S CMOS Sample-and-Hold Current Mode Circuit Using Double Sampling.". MEJ- Mansoura Engineering Journal, 25, 4, 2021, 42-49. doi: 10.21608/bfemu.2021.147060
HARVARD
El-Simary, H. (2021). 'A 80 MS/S CMOS Sample-and-Hold Current Mode Circuit Using Double Sampling.', MEJ- Mansoura Engineering Journal, 25(4), pp. 42-49. doi: 10.21608/bfemu.2021.147060
VANCOUVER
El-Simary, H. A 80 MS/S CMOS Sample-and-Hold Current Mode Circuit Using Double Sampling.. MEJ- Mansoura Engineering Journal, 2021; 25(4): 42-49. doi: 10.21608/bfemu.2021.147060
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