Performance Study of the Modified Fast Serial Parallel Multiplier with RECO Technique.

Document Type : Research Studies

Authors

1 Professor of Computer & Control Engineering Department., Faculty of Engineering., El-Mansoura University., Mansoura., Egypt.

2 Assistant Professor of Computer & Control Engineering Department., Faculty of Engineering.,El-Mansoura University., Mansoura., Egypt.

3 VTMS division Transit Department., Suez Canal Authority., Ismailia., Egypt.

Abstract

This paper studies the speed and hardware performance of the modified fast serial-parallel (MFSP) multiplier with concurrent error detection (CED) by REcomputing with Circularly shifted Operands (RECO) technique.  The MFSP multiplier has been proposed primarily to increase the speed of the fast serial parallel (FSP)multiplier by using fast parallel adder instead of the parallel ripple carry adder. This multiplier can be used for VLSI when the chip size is limited for high speed applications. By using RECO technique for CED applied to the MFSP multiplier, the copmromise between suitable error coverage, small error latency , suitable multiplication speed improvement and low hardware over-head as possible is expected. This multiplier is suitable for VLSI and can be used efficiently In digital signal processing (DSP) applications. Speed and hardware comparisons to the carry save-add shift (CSAS) multiplier with and without RECO technique are also made.

Main Subjects

MEJ- Mansoura Engineering Journal
Volume 19, Issue 3
VOL 19 has two issues issue 3 consist of two parts from (September to December)
September 1994
Pages 112-122

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